1. Technical Field
The present invention generally relates to a semiconductor element and more particularly to a fin-type field effect transistor.
2. Description of the Related Art
With the reduction of line width in metal oxide semiconductor (MOS) fabrication, leakage current in areas between the source and the drain away from the gate is increasingly significant. Although the leakage current can be reduced through a reduction in the thickness of the gate dielectric layer, it is no longer effective when the line width drops to 0.1 micrometer or below. To deal with this problem, Professor Chenming Hu of the University of California at Berkley has proposed two methods. The first method is to use an extremely thin first doping type semiconductor substrate to fabricate MOSFET so that the substrate no longer has an area away from the gate and hence a leakage current no longer exists. The second method is to use a double gate strip. A gate dielectric layer in the double gate strip surrounds the channel region so that the entire channel region is subjected to the influence of the gate electric field. Ultimately, the on current of the device is increased and the leakage current is reduced.
A fin-type field effect transistor (FinFET) that combines the two aforementioned concepts is provided. During the manufacturing process of the conventional FinFET, a plurality of trenches are formed on a doped silicon substrate to form a plurality of fin-type structures between the trenches. Or, a doped silicon layer is patterned to form the fin-type structures. Then, a gate insulating layer and a gate strip are formed on the fin-type structures to form a FinFET. The two ends of each fin-type structures are doped as a source region and a drain region of the FinFET. The portions of the fin-type structures are channel region of the FinFET. Accordingly, the channel widths of the FinFET are relative to the heights of the fin-type structures. For example, in double-gate FinFET, the channel width is equal to twice of the height of the fin-type structure; in tri-gate FinFET, the channel width is equal to twice of the height of the fin-type structure plus the width of the top of the fin-type structure.
However, the fin-type structures of the conventional FinFET all have the same height because of the manufacturing factors, so that the channel width of the FinFET is only decided by reducing or increasing the number of the fin-type structures. Therefore, it is difficult to manufacture FinFETs with proper channel width for any requests.